The present invention relates to semiconductor devices and, more particularly, to a trench-gated device having trench walls formed by selective epitaxial growth and a process for making the device.
An MOS transistor having a trench gate structure offers important advantages over a planar transistor for high current, low voltage switching applications. The DMOS trench gate typically includes a trench extending from the source to the drain and having sidewalls and a floor that are each lined with a layer of thermally grown silicon dioxide. The lined trench is filled with doped polysilicon. The structure of the trench gate allows less constricted current flow and, consequently, provides lower values of specific on-resistance. Furthermore, the trench gate makes possible a decreased cell pitch in an MOS channel extending along the vertical sidewalls of the trench from the bottom of the source across the body of the transistor to the drain below. Channel density is thereby increased, which reduces the contribution of the channel to on-resistance. The structure and performance of trench DMOS transistors are discussed in Bulucea and Rossen, xe2x80x9cTrench DMOS Transistor Technology for High-Current (100 A Range) Switching,xe2x80x9d in Solid-State Electronics, 1991, Vol. 34, No. 5, pp 493-507, the disclosure of which is incorporated herein by reference.
In addition to their utility in DMOS power devices, trench gates are also advantageously employed in insulated gate bipolar transistors (IGBTs), MOS-controlled thyristors (MCTs), and other trench-gated devices. A typical semiconductor device contains an array of MOSFET structures arranged in various cellular or stripe layouts currently used by the industry.
The trench gate of a MOSFET is typically formed by plasma etching a trench into a substrate and lining the trench with a dielectric material prior to substantially filling it with a conductive material. As required device dimensions become smaller, the surface roughness of the etched trench sidewall becomes increasingly important because of its effect on the threshold voltage and reliability of the device. The improved smoothness of the sidewalls in a device of the present invention provides an improvement in the efficiency and power handling capability of the device.
The present invention is directed to an improved trench-gated power device comprising a substrate having an overlying layer of epitaxial material disposed on an upper layer of the substrate, well regions containing source and body regions, a trench gate, and a drain region, wherein the improvement comprises a gate trench having beneficially smooth sidewalls that comprise selectively grown epitaxial material and body regions that are recessed with respect to adjacent source regions.
Further in accordance with the present invention is a process for forming an improved trench-gated power device. A dielectric layer having an upper surface and thickness and width dimensions that substantially correspond to the height and width dimensions of a gate trench is formed on an upper layer of a substrate. A layer of epitaxial material is grown on the upper layer of the substrate and the dielectric layer and planarized to be substantially coplanar with the upper surface of the dielectric layer, which is then removed, thereby forming gate trench sidewalls that comprise selectively grown epitaxial material. The process further comprises lining the trench with a dielectric material and substantially filling the lined trench with a conductive material, thereby forming a trench gate, and forming well, body, and source regions in the planarized epitaxial material.